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Please use this identifier to cite or link to this item: http://hdl.handle.net/10525/1176

Title: Using SAT for Combinational Implementation Checking
Authors: Cheremisinova, Liudmila
Novikov, Dmitry
Keywords: Design Automation
Verification
Simulation
SAT
Issue Date: 2008
Publisher: Institute of Information Theories and Applications FOI ITHEA
Abstract: The problem of checking whether a system of incompletely specified Boolean functions is implemented by the given combinational circuit is considered. The task is reduced to testing out if two given logical descriptions are equivalent on the domain of one of them having functional indeterminacy. We present a novel SAT-based verification method that is used for testing whether the given circuit satisfies all the conditions represented by the system of incompletely specified Boolean functions.
URI: http://hdl.handle.net/10525/1176
ISSN: 1313-0455
Appears in Collections:Book 7 Artificial Intelligence and Decision Making

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